Technical article - title:
Power For Processors At Minimal Cost
(Written for Analog Devices)

[Equations that appeared in the article have placeholders here due to limitations in showing mathematical notation]

New processors demand more from their power supplies - fast load steps, tight load-line constraints, and fast output changes. A power supply design using an existing controller would be preferable, but it also needs to meet the latest load step specifications with low ripple. Older controllers can't provide load steps directly through inductors. They need more bulk capacitors to smooth transients. Power supply size requirements are unchanged, so more capacitors won't fit. What are the alternatives?

Same Controller, Different Inductors and Capacitors?
Take a closer look at using an existing controller first. Start with peak ripple current, a desired output voltage, and the number of phases. For a desktop application and some bigger laptops, four phases give the fastest response to load steps with the smallest ripple current. You'll need a switching frequency high enough to respond to load transients at the required slew rate. You'll also need more costly MOSFETs to keep RDSON low and minimize switching loss at the higher frequency.

For the higher switching frequency to help, you'll need more bandwidth in the controller's feedback loops to respond fast enough. But is the controller stable for those wider bandwidths? Older controllers probably aren't.

So existing controllers force lower bandwidth. Higher switching frequency makes no sense in that case, since lower bandwidth limits the loop response anyway. The inductors won't be supplying large current steps, so more bulk capacitors will be needed. This is expensive in cost and board area. And there's an upper limit on bulk capacitance. Too much won't let the supply respond in time to on-the-fly output voltage stepping.

New Controllers For New Problems
New multiphase synchronous buck controllers solve these problems. Their stable feedback loops at high speed permit smaller designs at lower cost.

Properly compensated, a high-bandwidth controller handles maximum load steps without oscillation. You need less charge from bulk capacitors, since the controller provides more current from the inductors. New controller architectures respond quickly to current transients, turning on multiple phases at a time. This increases the available current to handle the load without additional bulk capacitance. The best controllers respond to increased current demands without the built-in delays of older single-edge control architectures. With the controller handling big load steps, inductor, capacitor, and MOSFET choices are fairly straightforward. Consider component selection, and then look at the controller.

A typical Voltage Regulator-Down (VRD) supply for a desktop CPU has these requirements: Input voltage VIN = 12 V, output set voltage VVID = 1.3 V, duty cycle D = 0.108, no-load output = 1.285 V, output with 115-A load = 1.170 V, load line RO for 115 mV static output drop from no-load to full-load = 1.0 m , maximum output current = 130 A, maximum output current step Io = 100 A, maximum output slew rate SR = 200 A/us.

Choose four phases to meet the high-current requirements. 330 kHz switching frequency per phase is a good trade-off between switching losses, ripple and output filter size, though some controllers will go higher.

Inductor First
Begin by calculating the inductor value. The classic buck regulator equation gives

VVID = VIN * D (1)

This is a good reminder that inductor value L doesn't affect the regulator's output voltage VVID.

Inductor value choice depends on output ripple requirements. If RO is the load line, and the ripple voltage due to inductor ripple current is VRIPPLE,

[INSERT INDUCTOR VALUE EQUATION] (2)

Pick a peak-to-peak inductor ripple current that's less than half of the inductor's maximum dc current. An 11-A ripple current gives 7 mVPP ripple voltage with a 1.0-m load line. For a VRD supply with number of phases n equal to four, and FSW = 330 kHz, equation (2) gives L 320 nH.

If ripple is lower in the actual design, use a smaller inductor. The inductor shouldn't saturate at peak 35.5A current per phase, and should handle the power dissipation from core loss and the average 30A winding current. The smallest possible inductor value reduces the number of output capacitors.

The dc resistance (DCR) of the inductor affects current sensing in many controller designs. Choose a compromise value to avoid power losses but give good current measurement accuracy. A good choice is DCR about ½ to 1 ½ times RO, depending on the controller.

Minimizing Output Capacitance
Ceramic and bulk capacitors perform different jobs at the output of a switching regulator system. Ceramic capacitors take care of high-frequency transients at the CPU. They need to be inside the CPU socket for best transient suppression, so you're limited by how many surface-mount capacitors will fit. If more are needed, place them alongside the socket.

The worst-case fast transient is a maximum load step right after a switching cycle stops. Look at the switching on-time, maximum output current step and maximum output slew rate to choose the needed RC time-constant at the CPU power pins. Equation (3) gives a lower limit for ceramic capacitance Cz.

[INSERT CERAMIC CAPACITOR EQUATION] (3)

For VRD requirements, CZ should be at least 180uF. Eighteen 10 uF ceramic capacitors will do it. Variations in PC board parasitics and bulk capacitor parasitics may change the amount of ceramic capacitance needed.

Aside from the high cost and large board space, just throwing a bunch of bulk capacitance at low-frequency output filtering won't work. The need to change VVID on the fly imposes an upper limit - the supply needs to make a voltage step Vv in time tv with a specified error VERR. The output needs a minimum capacitance for smooth load release with the maximum load step Io and the maximum allowable overshoot - that's the lower limit.

With a maximum allowable overshoot Vrl, the load release voltage is

[INSERT RIPPLE VOLTAGE EQUATION] (4)

These equations define the limits on bulk capacitors Cx:

[INSERT Cxmin EQUATION] (5)

[INSERT Cxmax EQUATION] (6)

with K = -ln (VERR / VV)

To meet the equations, the bulk capacitor bank's effective series resistance (ESR) should be less than two times the droop resistance Ro. If the equations give Cxmin larger than Cxmax, use a smaller inductor or more phases to meet the VVID step specification. To keep the same output ripple with a smaller inductor, you'll have to increase the switching frequency.

With CZ = 180 uF, an on-the-fly 450 mV step in 230 us, a 50 mV overshoot limit and 2.5 mV settling error, you get a range of 3.92 mF to 43 mF for bulk capacitor Cx. Ten 560-uF aluminum-poly capacitors with typical 6-milliohms ESR each gives a 5.6 mF total with paralleled ESR of 0.6 milliohms

Make a final check on effective series inductance (ESL), of the bulk capacitors to be sure it's low enough to limit high-frequency ringing during a load step. You need

ESL < CZ * Ro2 * Q2, with Q2 limited to 4/3 for a critically-damped system.

This gives ESL 240 pH. If the bulk capacitor bank's ESL is too large, increase the number of ceramic capacitors or use lower ESL bulk capacitors to limit undershoot.

MOSFET Choices
MOS power devices in buck supplies need low RDSON to minimize conduction losses and power dissipation. They also need low input capacitance to minimize turn-on time. A faster device with less CISS has higher RDSON, so a compromise is necessary. 12 V VIN gives a 10 V minimum gate drive from the Analog Devices ADP3120A dual MOSFET driver, so logic-level threshold MOSFETs are a good choice.

Conduction dominates synchronous MOSFET power losses. Equation (7) shows synchronous device I2R dissipation from main and ripple currents.

Synchronous MOSFETs can accidentally turn on if their reverse transfer capacitance CRSS couples enough charge to the gate when the switch node goes high. This results in shoot-through with both main and synchronous devices on. Use a one to ten or lower ratio of feedback capacitance CRSS to input capacitance CISS in the synchronous devices to prevent it.

Turn-off time for synchronous MOSFETs should be less than the non-overlapping dead time of each phase's MOSFET driver. Analog Device's ADP3120A has a 2 output impedance and 45-ns typical dead time. Using a MOSFET with typical 1- gate resistance and keeping 2.5 RINCISS less than 45 ns gives an upper limit of 6000 pF on total gate capacitance. With two paralleled synchronous MOSFETs, gate capacitance of each should be less than 3000 pF.

High-side (main) MOSFETs need to handle power dissipation from conduction currents and switching losses. Switching loss comes from MOS turn-on and turnoff times, so main MOSFET input capacitance needs to be lower than for the synchronous MOSFETs. Equations (8) and (9) show the tradeoffs between controller FSW, CISS and RDSON for main MOSFETs.

Conduction losses for synchronous and main MOSFETs follow similar equations. The difference is in duty cycle, since synchronous and main MOSFETs have complementary on-times.

If nsf is the number of synchronous MOSFETs and n is the number of phases, synchronous MOSFET conduction loss is

[INSERT SYNCHRONOUS MOSFET CONDUCTION LOSS EQUATION] (7)

Conduction loss for main MOSFETs with the number of devices equal to nmf is

[INSERT MAIN MOSFET CONDUCTION LOSS EQUATION] (8)

Equation (9) describes the main MOSFETs' additional dissipation from switching. If the total input resistance from the gate driver and MOSFET is Rg, a good approximation to the switching power is

[INSERT MAIN MOSFET SWITCHING LOSS EQUATION] (9)

For D-PAK MOSFETs up to a 50ºC ambient temperature, 1 W to 1.5 W total dissipation gives a safe 120ºC junction temperature.

The last thing to check is the driver dissipation for each phase. This is the total of each driver's standby power Icc*VIN, and power from current needed to supply each driven MOSFET's gate charge. With synchronous gate charge Qgsf, main gate charge Qgmf, and driver standby current Icc, the equation is

[INSERT DRIVER POWER DISSIPATION EQUATION] (10)

This should be less than the driver's dissipation limit at the highest ambient temperature.

Input Capacitor Recommendations
The high-side MOSFET's drain current is a rough square wave with a duty ratio equal to n * Vout / Vin and amplitude of the maximum output current times 1/n. Low-ESR input capacitors, sized for the maximum rms current, must be used to filter ripple at the input. This rms current is

[INSERT RMS INPUT CAPACITOR CURRENT EQUATION] (11)

With the chosen parameters, equation (11) gives Icrms equal to 14.74 A.

Capacitor manufacturers' current ratings may be based on only 2,000 hours of life, so use capacitors with ratings higher than the calculated Icrms. Paralleled ceramic and electrolytic capacitors will be necessary to smooth high- and low-frequency transients.

Input capacitor value depends on how much ripple is okay, and there are several contributors. Capacitor voltage from the integral of ac current is one. A starting point with a required input ripple voltage Vin_rpl is

[INSERT INPUT CAPACITOR STARTING POINT EQUATION HERE] (12)

More ripple comes from capacitor ESR and AC current. Minimize this IR drop with low ESR to meet system requirements.

Controller Speed
What controller bandwidth do you really need? It depends on the application. The controller system and its output decoupling should have a resistive impedance over the widest possible range. That output resistance should match the load line. Bandwidths of the controller's voltage error amplifier and current sense amplifier should be wide enough to let the inductor and output capacitors dominate the response.

Controller speed is more straightforward. The controller needs to respond to maximum load steps and load releases transparently. Older architectures with excessive turn-on delays for each phase aren't fast enough. The controller, drivers and MOSFETs also need to be fast enough to meet on-the-fly VVID change specifications.

Older single-edge designs wait until the next clock cycle to respond if the transient happens while the controller is inactive. Most of them clock only one phase at a time, forcing the power supply to provide current from its bulk capacitors. When a single-edge controller catches up, it can typically only power up two phases at most.

Recent controller architectures use asynchronous correction to reduce load step response time with fewer capacitors. They can turn on all phases at once to supply CPU current demands. There's no built-in clock delay for a response, either.

Synchronous buck controllers like the Analog Devices ADP3192 sense on-the-fly load changes. The ADP3192 re-starts phases in sync with the load step to supply maximum current without waiting. Its typical response time to a worst-case load step is 300 Ns Since the extra current goes into the load and normal multiphase operation follows after the initial load step demand is satisfied, ripple doesn't increase.

There are other controller architectures which turn on all phases at once to handle large load steps. Most of them use a linear transfer characteristic to process load changes and control outputs. The ADP3192 uses nonlinear gain to respond to load steps. Large signals from a maximum load step hit the high-gain part of its transfer curve to turn on all output phases. Smaller load steps at the low-gain part of the curve cause normal PWM changes to individual phases. This gives better noise immunity and low jitter, since most noise will be on the small-signal, low-gain part of the transfer curve. Controllers with a constant high gain are much more susceptible to noise.

Desktop applications need four-phase supplies, but controllers like the ADP3192 can easily be configured for two or three phases for small laptops and other low-power applications. Inductor and output capacitor values can easily be calculated with a smaller number of phases n.

Figure 1 shows an all-phases-on response to a load step. Three phases were used in this example.

Good controllers support thermal overload protection and compensation for component temperature variation. The ADP3192 sets control outputs to turn on a fan or shut down the supply at temperatures set by thermistors at a thermal sense input. It's easy to add other thermistors to compensate for the temperature coefficient of the inductor's DCR for more accurate current sensing.

A circuit example appears in Figure 2.

Figure 1 - Controller response to load step using ADP3192 and ADP3120, three phases [Insert scope photo]

Figure 2 - [Insert application schematic from ADP3192 data sheet]